In recent years, DRAM-embedded devices in which a high-performance logic circuit and a DRAM memory are combined together have been made practical for multimedia devices requiring miniaturization, a high memory capacity and a high data transfer rate. The DRAM-embedded devices are broadly classified into a trench capacitor type in which a capacitor as an information storage unit of a DRAM memory cell is provided in a trench of a semiconductor substrate and a stack capacitor type in which a capacitor and an electrode are three-dimensionally stacked above a principal surface of a semiconductor substrate.
On the other hand, attention is again focused on a device in which a so-called planar (MOS structure) DRAM and a logic circuit are merged using a gate dielectric as a capacitance dielectric and a gate electrode as a plate electrode, because it is a device in which a memory cell can be formed more easily.
Problems to be Solved
However, the above-described known merged DRAM/logic devices have the following problems.
Processes for fabricating the trench-capacitor-type and stack-type merged DRAM/logic devices additionally involve complicated process steps to form a memory cell capacitor as well as a memory cell transistor. Consequently, the yield enhancement of the devices becomes increasingly difficult in addition to prolonging the development period for design changes or the like and the period required for fabrication of the devices, leading to an increase in production cost.
In regard to a planar-type merged DRAM/logic device, although a process for fabricating the same is short and simple, the size of the memory cell becomes larger than that of the stack capacitor type or the trench capacitor type. Therefore, it becomes hard to obtain a denser semiconductor device while embedding a high-capacity DRAM in a logic circuit.